(a) Field of the Invention
The invention relates to a digital frequency comparator and, more particularly, to a frequency comparator employing relatively few elements for clock-pulse recovery with xe2x80x9cnon-return-to-zero dataxe2x80x9d
(b) Description of the Related Art
FIG. 1 shows the clock-pulse of a phase-frequency locked loop 100 of non-return zero (NRZ) data with respect to the conventional technique, as described in Mehmet Soyuer, Herschel A. Ainspan and John F. Ewen, xe2x80x9cA1.6 Gb/s Phase-Frequency Locked Loop For Timing Recoveryxe2x80x9d, IEEE International Symposium on Circuits and System, Vol. 1, 1995 p.p. 187-190.
The phase-frequency locked loop 100 includes a digital phase-frequency detector (DPFD) 101, charge pumps/loop filters (CPF) 102 and 103, a V-I converter 104, and a voltage-controlled oscillator (VCO) 105. It is to be noted that the V-I converter usually is part of the VCO. However, the V-I converter is shown explicitly in FIG. 1, thus the 105 actually is a current-controlled oscillator. Besides, the resistor and capacitor are part of the loop filter shown explicitly.
The digital phase-frequency detector 101 is used to receive NRZ data and the output of the clock pulse of the voltage-controlled oscillator 105, and output the control signal UP or DOWN to the charge pump/loop filter 102 in the case of either the output clock pulse frequency being lower or higher than the transmission frequency of the data signal. The charge pump/loop filter 102 outputs a control voltage to the voltage-controlled oscillator 105 based on the control signal UP or DOWN, so as to control the output clock pulse of the voltage-controlled oscillator 105. The phase-locked loop 100 generates a reference clock pulse synchronized with the NRZ data to latch the time latch 106 in order to output accurate data.
FIG. 2 shows the circuit diagram of the phase-frequency detector 101 of FIG. 1. As shown in FIG. 2, the phase-frequency detector 101 includes eight flip-flops 1011, four NOR gates 1012 and two OR gates 1013. The eight flip-flops 1011 are connected in series and are divided into four groups. Each of the output signals generates the control signal UP or DOWN via the logic circuit of NOR gate 1012 and OR gate 1013. The design of the flip-flop requires relatively more logic gates combination and contains a time sequence control signal. Thus, if the number of the flip-flops can be reduced, the logic elements can also be decreased so as to lower the production cost, and the response speed is also increased.
Accordingly, it is an object of the invention to provide a digital frequency comparator having relatively few elements being used in the non-return zero data transmission for clock pulse recovery.
Another object of the invention is to provide a digital frequency comparator which requires relatively few elements for clock-pulse recovery and lowers the cost of production and also increases the processing speed.
To attain the above-mentioned objects, the invention provides a digital frequency comparator including a first double-edge triggered D flip-flop, a second double-edge triggered D flip-flop, and a combination logic. Firstly, the first double-edge triggered D flip-flop receives a data signal and a first reference clock signal, then makes use of the positive-and-negative triggering to output a first state signal and a second state signal of the first reference clock signal. Secondly, the second double-edge triggered D flip-flop receives a data signal and a second reference clock signal, then makes use of the positive-and-negative triggering to output a first state signal and a second state signal of the second reference clock signal. The phase angle of the second reference clock signal is 90-degree lagging behind the phase angle of the first reference clock signal. Lastly, the combination logic receives the first state signal and the second state signal of the first double-edge triggered D flip-flop and the second double-edge triggered D flip-flop. Afterward, the combination logic enables an UP pulse when the frequency of the data signal transmission clock is faster than the frequency of the first reference clock signal. Conversely, the combination logic enables a DOWN pulse when the frequency of the data signal transmission clock is slower than the frequency of the first reference clock signal.
The first double-edge triggered flip-flop includes a first D-type flip-flop, a second D-type flip-flop, a first multiplexer, and a second multiplexer. The first D-type flip-flop has a D-input end receiving the first reference clock pulse. The data signal is used as the positive trigger. The second D-type flip-flop has a D-input end receiving the first reference clock pulse. The reverse of the data signal is used as the positive trigger. The first multiplexer connects to the Q output ends of the first D-type flip-flop and the second D-type flip-flop. Using the reverse of the data signal as a selecting signal, the first multiplexer provides the output of the first D-type flip-flop when the data signal is 1, and the output of the second D-type flip-flop when the data signal is 0. The second multiplexer connects to the Q output ends of the first D-type flip-flop and the second D-type flip-flop. Using the data signal as a selecting signal, the second multiplexer provides the output of the first D-type flip-flop when the data signal is 0, and the output of the second D-type flip-flop when the data signal is 1.
The invention can improve the processing speed with a high bit rate at relatively low cost since the invention uses the very simple combination logic and the double-edge triggered D flip-flops.